LEADER 00000nam a2200289 a 4500
001 u31888
001 32633
003 SIRSI
005 20110525184200.0
008 250511s2011 xxua00000b0000001100eng0d
020 9780136019282 (alk. paper)
020 0136019285 (alk. paper)
020 0130891614 (alk. paper)
020 9780130891617 (alk. paper)
049 JURF
050 00 TK7885.7|bC5485 2011
100 1 Ciletti, Michael D
245 10 Advanced digital design with the Verilog HDL /|cMichael D.
Ciletti.
250 2nd ed
260 Boston :|bPrentice Hall,|c2011
300 xviii, 965 p. :|bill. ;|c24 cm.
490 00 Prentice Hall Xilinx design series
504 Includes bibliographical references and indexes.
650 0 Logic design|xData processing
650 0 Verilog (Computer hardware description language)
Female Library
|
TK7885.7 C5485 2011 |
Available |
|